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Espressif Systems /ESP32-P4 /I2C0 /CLK_CONF

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Interpret as CLK_CONF

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31282724232019161512118743000000000000000000000000000000000000000000SCLK_DIV_NUM0SCLK_DIV_A0SCLK_DIV_B0 (SCLK_SEL)SCLK_SEL0 (SCLK_ACTIVE)SCLK_ACTIVE

Description

I2C CLK configuration register

Fields

SCLK_DIV_NUM

the integral part of the fractional divisor for i2c module
SCLK_DIV_A

the numerator of the fractional part of the fractional divisor for i2c module
SCLK_DIV_B

the denominator of the fractional part of the fractional divisor for i2c module
SCLK_SEL

The clock selection for i2c module:0-XTAL,1-CLK_8MHz.
SCLK_ACTIVE

The clock switch for i2c module

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data